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9-33 features ? ets 300-012, ccitt i.430 and ansi t1.605 s/t interface ? full-duplex 2b+d, 192 kbit/s transmission ? link activation/deactivation ? d-channel access contention resolution ? point-to-point, point-to-multipoint and star con?gurations ? master (nt)/slave (te) modes of operation ? exceeds loop length requirements ? complete loopback testing capabilities ? on chip hdlc d-channel protocoller ? 8 bit motorola/intel microprocessor interface ? controllerless or microprocessor-controlled operation ? mitel st-bus interface ? low power cmos technology ? single 5 volt power supply applications ? isdn nt1 ? isdn s or t interface ? isdn terminal adaptor (ta) ? digital sets (te1) - 4 wire isdn interface ? digital pabxs, digital line cards (nt2) description the mt8930c subscriber network interface circuit (snic) implements the etsi ets 300-012, ccitt i.430 and ansi t1.605 recommendations for the isdn s and t reference points. providing point-to- point and point-to-multipoint digital transmission, the snic may be used at either end of the subscriber line (nt or te). an hdlc d-channel protocoller is included and controlled through a motorola/intel microprocessor port. a controllerless mode allows the snic to operate without a microprocessor. the mt8930c is fabricated in mitels cmos process. figure 1 - functional block diagram dsti dsto f0od c4b f0b star/ rsto ck/nt cmode ltx vbias lrx v dd v ss st-bus interface timing and control d-channel priority mechanism pll hdlc transceiver s-bus link interface link activation controller microprocessor interface rsti half ad0-7 r/ w/ wr, aft/pri ds/ rd, dinb as/ale, p/ sc cs, dreq irq/ nda, dcack ordering information mt8930ce 28 pin plastic dip mt8930cp 44 pin plcc -40 c to +85 c issue3 november 1997 mt8930c subscriber network interface circuit cmos st-bus ? family
mt8930c 9-34 figure 2 - pin connections pin description pin # name description dip plcc 1 2 half half input/output: this is an input in nt mode and an output in te mode identifying which half of the s-interface frame is currently being written/read over the st-bus (half = 0 sampled on the falling edge of c4b within the frame pulse low window, identi?es the information to be transmitted/received in the ?rst half of the s-bus frame while half = 1 identi?es the information to be transmitted/received into the second half of the s-bus frame). tying this pin to v ss or v dd in nt mode will allow the device to free run. this signal can also be accessed from the st-bus c-channel. 23 c4b 4.096 mhz clock: a 4.096 mhz st-bus data clock input in nt mode. in te mode, a 4.096 mhz output clock phase-locked to the line data signal. 34 f0b frame pulse: an active low frame pulse input indicating the beginning of active st- bus channel times in nt mode. frame pulse output in te mode. 47 f0od delayed frame pulse output: an active low delayed frame pulse output indicating the end of active st-bus channels for this device. can be used to daisy chain to other st-bus devices to share an st-bus stream. 5 8 dsti data st-bus input: a 2048 kbit/s serial pcm/data st-bus input with d, c, b1, and b2 channels assigned to the ?rst four timeslots. these channels contain data to be transmitted on the line and chip control information. 6 9 dsto data st-bus output: a 2048 kbit/s serial pcm/data st-bus output with d, c, b1 and b2 channels assigned to the ?rst four timeslots respectively. the remaining timeslots are placed into high impedance. these channels contain data received from the line and chip status information. 7 13 cmode controller mode select input: when high, microprocessor control is selected. when low the controllerless mode is enabled and the microport pins are rede?ned as control inputs and status outputs. 8 14 ck/nt te clock/network termination mode select input. for te mode, this pin must be tied to v ss or to a 4.096 mhz clock (a clock is required for standard isdn te applications). for nt mode, this pin must be tied to v dd . refer to st-bus interface section for further explanation. a pull-up resistor is needed when driven by a ttl device. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 half c4b f0b f0od dsti dsto cmode ck/nt r/ w/ wr, aft/pri ds/ rd, dinb as/ale, p/ sc cs, dreq irq/ nda, dcack vss vdd vbias ltx lrx star/ rsto rsti ad7, dr ad6, ar ad5, m/s ad4, mch ad3, mfr ad2, sync/ba ad1, is1 ad0, is0 28 pin pdip 44 pin plcc nc nc c4b f0b half vdd vbias ltx nc lrx nc star/ rsto rsti nc ad7, dr ad6, ar nc ad5, m/s ad4, mch ad3, mfr nc f0od dsti dsto nc nc nc cmode ck/nt nc r/ w/ wr, aft/pri ds/ rd, dinb nc as/ale, p/ sc cs, dreq irq/ nda, dcack vss ad0, is0 ad1, is1 ad2, sync/ba nc nc nc nc 1 65432 44434241 40 7 8 9 10 11 12 13 14 15 16 39 38 37 36 35 34 33 32 31 30 23 18 19 20 21 22 24 25 26 27 28 17 29
mt8930c 9-35 916r/ w / wr aft/pri read/ write or write input (cmode = 1): de?nes the data bus transfer as a read (r/ w=1) or a write (r/ w=0) in motorola bus mode. rede?ned to wr in intel bus mode. adaptive-fixed timing/priority select input (cmode=0) : in nt mode, causes the pll and rx ?lters and peak detectors to be disabled in favour of ?xed timing and ?xed thresholds for short passive bus operation (0=?xed, 1=adaptive). in te mode, this is the priority input. high priority (pri=1) is normally reserved for signalling. 10 17 ds/ rd dinb data strobe/read input (cmode = 1): active high input indicates to the snic that valid data is on the bus during a write operation or that the snic must output data during a read operation in motorola bus mode. rede?ned to rd in intel bus mode. d-channel in b1 timeslot input (cmode = 0): active high input that causes all eight st-bus d-channel bits, instead of the usual two bits, to be routed to and from the s-interface b1 timeslot. when active, marks are transmitted in the s-interface d-channel. 11 19 as/ale p/ sc address strobe/address latch enable input (cmode = 1): in motorola bus mode the falling edge is used to strobe the address into the snic during microprocessor access. rede?ned to ale in intel bus mode. parallel/serial control input (cmode = 0): determines if the serial c-channel ( p / sc=0) or microport pins (p/ sc=1) are the source of chip control when controllerless mode is selected. if the st-bus is chosen as the source, the dedicated control input pins are ignored but the status output pins remain valid. 12 20 cs dreq ic chip select input (cmode=1): active low input used to select the snic for microprocessor access . d-channel request input (cmode = 0): an active high input that in te mode only causes the snic to transmit a 01111110 ?ag immediately if the d-channel is free, or wait until it becomes available and then transmit the ?ag. the dcac k signals the successful acquisition of the d-channel. if dreq is tied low, continuous ones are transmitted in the s-bus d-channel. internal connection (cmode = 0): tie to v ss for normal operation in nt mode only. 13 21 irq nd a dcac k ic interrupt request (open drain output) (cmode = 1): an output indicating an unmasked hdlc interrupt. the interrupt remains active until the microprocessor clears it by reading the hdlc interrupt status register. this interrupt source is enabled with b2=0 of master control register. new data available (open drain output) (cmode = 1): an active low output signal indicating availability of new data from the s-bus. this signal is selected with b2=1 of master control register. d-channel acknowledge (open drain output) (cmode = 0): in te mode only indicates that the snic has gained access to the d-channel in response to a dreq and has transmitted the ?rst zero of an opening ?ag. the user should immediately begin transmitting the rest of the packet over the st-bus d-channel. if this signal goes high in the middle of transmission, the te has lost the bus and must regain access of the d- channel before retransmitting the packet. internal connection (open drain output) (c-mode=0). this pin is not used in nt mode and should be left disconnected. this pin must be tied to v dd with a 10k w resistor. 14 22 v ss ground. 15- 22 24-26 30-32 34-35 ad0-7 bidirectional address/data bus (cmode = 1): electrically and logically compatible to either intel or motorola micro-bus speci?cations. if ds/ rd is low on the rising edge of as/ale then the chip operates to motorola specs. if ds/ rd is high on the rising edge of as/ale intel mode is selected. taking rsti low sets motorola mode. 15- 16 24- 25 is0-is1 internal state outputs (cmode =0): binary encoded state number outputs. is0 is1 nt mode te mode 0 0 deactivated deactivated 0 1 pending deactivation synchronized 1 0 pending activation activation request 1 1 activated activated pin description (continued) pin # name description dip plcc
mt8930c 9-36 17 26 sync/ba synchronization/bus activity output (cmode = 0): output indicating synchronization to incoming rx frames when activation request is asserted and the deactivation request is 0 (ar = 1 and dr = 0). synchronization is declared once three successive frames conforming to the 14-bit bipolar violation criteria have been detected. if part is deactivated or activation request is 0 (ar = 0 or dr = 1), this pin indicates the presence of bus activity. 18 30 mfr multiframe input/output (cmode=0): multiframe input in nt mode or output in te mode. setting this pin to one in nt mode when half = 1, forces the f a , n pair to 1, 0 respectively. this pin going high in te mode indicates that f a = 1 & n= 0 has been received. this signal is updated on the rising edge of the half signal. 19 31 mch maintenance channel (q-channel) input/output (cmode=0): an output in nt mode which is valid only in the frame following the transmission of mfr. in te mode, this is the maintenance channel (q-channel) input which is transmitted in the f a and l bits following the reception of the multiframe signal. this input is sampled on the falling edge of the half signal. 20 32 m/s m/s input/output (cmode=0): m/s bit input in nt mode or m/s bit output in te mode. m is read or written when half=1 while s is read or written when half=0. 21 34 ar activate request input (cmode = 0): asserting ar with dr = 0 will initiate the appropriate s-interface activation sequence coded in the nt or te activation/ deactivation controller. 22 35 dr deactivate request input (cmode = 0): asserting dr high will initiate the appropriate s-interface deactivation sequence coded in the nt or te activation/ deactivation controller. 23 37 rsti reset input: schmitt trigger reset input. if 0, sets all control registers to the default conditions, resets activation state machines to the deactivated state, resets hdlc, clears the hdlc fifos. sets the microport to motorola bus mode. 24 38 star/ rsto star/reset (open drain output): 192kbit/s rx data output ?xed relative to the st- bus timebase. a group of nts, in ?xed timing mode, can be wire ored together to create a star con?guration. active low reset output in te mode indicating 128 consecutive marks have been received. can be connected directly to rsti to allow nt to reset all tes on the bus. this pin must be tied to v dd with a 10 k w resistor. 25 40 lrx receive line signal input: this is a high impedance input for the pseudoternary line signal to be connected to the line through a 2:1 ratio transformer. see figures 20 and 21. a dc bias level on this input equal to v bias must be maintained. 26 42 ltx transmit line signal output: this is a current source output designed to drive a nominal 50 ohm line through a 2:1 ratio transformer. see figures 20 and 21. 27 43 v bias bias voltage: analog ground for tx and rx transformers. this pin must be decoupled to v dd through a 10 m f capacitor with good high frequency characteristics (i.e., tantalum). 28 44 v dd power supply input. 1,5-6,10- 12,15,18, 23,27- 29, 33, 36, 39, 41 nc no connection. pin description (continued) pin # name description dip plcc
mt8930c 9-37 functional description the mt8930c subscriber network interface circuit (snic) is a multifunction transceiver providing a complete interface to the s/t reference point as speci?ed in ets 300-012, ccitt recommendation i.430 and ansi t1.605. implementing both point-to-point and point-to-multipoint voice/data transmission, the snic may be used at either end of the digital subscriber loop. a programmable digital interface allows the mt8930c to be con?gured as a network termination (nt) or as a terminal equipment (te) device. the snic supports 192 kbit/s (2b+d + overhead) full duplex data transmission on a 4-wire balanced transmission line. transmission capability for both b and d channels, as well as related timing and synchronization functions, are provided on chip. the signalling capability and procedures necessary to enable customer terminals (tes) to be activated and deactivated, form part of the mt8930cs functionality. the snic handles d-channel resource allocation and prioritization for access contention resolution and signalling requirements in passive bus line con?gurations. control and status information allows implementation of maintenance functions and monitoring of the device and the subscriber loop. an hdlc transceiver is included on the snic for link access protocol handling via the d-channel. depacketized data is passed to and from the transceiver via the microprocessor port. two 19 byte deep fifos, one for transmit and one for receive, are provided to buffer the data. the hdlc block can be set up to transmit or receive to/from either the s-interface port or the st-bus port. further, the transmit destination and receive source can be independently selected, e.g., transmit to s-interface while receiving from st-bus. the transmit and receive paths can be separately enabled or disabled. both, one and two byte address recognition is supported by the snic. a transparent mode allows data to be passed directly to the d channel without being packetized. a block diagram of the mt8930c is shown in figure 1. the snic has three interface ports: a 4-wire ccitt compatible s/t interface (subscriber loop interface), a 2048 kbit/s st-bus serial port, and a general purpose parallel microprocessor port. this 8-bit parallel port is compatible with both motorola or figure 3 - snic pin connections in various modes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 half c4bi f0bi f0od dsti dsto cmode nt r/ w/ wr ds/ rd as/ale cs irq, nda vss vdd vbias ltx lrx star rsti ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 half c4bo f0bo f0od dsti dsto cmode ck r/ w/ wr ds/ rd as/ale cs irq, nda vss vdd vbias ltx lrx rsto rsti ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 half c4bi f0bi f0od dsti dsto cmode nt aft dinb p/ sc ic ic vss vdd vbias ltx lrx star rsti dr ar m/si mcho mfri sync/ba is1 is0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 half c4bo f0bo f0od dsti dsto cmode ck pri dinb p/ sc dreq dcack vss vdd vbias ltx lrx rsto rsti dr ar m/so mchi mfro sync/ba is1 is0 nt mode nt mode te mode te mode controller mode controllerless mode
mt8930c 9-38 figure 4 - st-bus channel assignment d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 c7 c6 c5 c4 c3 c2 c1 c0 c7 c6 c5 c4 c3 c2 c1 c0 b1 b1 b1 b1 b1 b1 b1 b1 b2 b2 b2 b2 b2 b2 b2 b2 b1 b1 b1 b1 b1 b1 b1 b1 b2 b2 b2 b2 b2 b2 b2 b2 channel 1 (c) channel 2 (b1) channel 3 (b2) channel 0 (d) only valid with 64 kbit/s d-channel output in high impedance state dont care f0b dsti dsto f0od intel microprocessor bus signals and timing. the snic also has provisions for a controllerless mode (cmode=0), where the microprocessor port is rede?ned to allow access to the control/status registers via external hardware. the three major blocks of the mt8930c, consisting of the system serial interface (st-bus), hdlc transceiver, and the digital subscriber loop interface (s-interface) are interconnected by high speed data busses. data sent to and received from the s-interface port (b1, b2 and d channels) can be accessed from either the parallel microprocessor port or the serial st-bus port. this is also true for snic control and status information (c-channel). depacketized d-channel information to and from the hdlc section can only be accessed through the parallel microprocessor port. s-bus interface the s-bus is a four wire, full duplex, time division multiplexed transmission facility which exchanges information at 192 kbit/s rate including two 64 kbit/s pcm voice or data channels, a 16 kbit/s signalling channel and 48 kbit/s for synchronization and overhead. the relative position of these channels with respect to the st-bus is shown in figures 4 and 5. the snic makes use of the ?rst four channels on the st-bus to transmit and receive control/status and data to and from the s-interface port. these are the b, d and c-channels (see figure 4). the b1 and b2 channels each have a bandwidth of 64 kbit/s and are used to carry pcm voice or data across the network. the d-channel is primarily intended to carry signalling information for circuit switching through the isdn network. the snic provides the capability of having a 16 kbit/s or full 64 kbit/s d-channel by allocating the b1-channel timeslot to the d-channel. access to the depacketized d-channel is only granted through the parallel microprocessor port. the c-channel provides a means for the system to control and monitor the functionality of the snic. this control/status channel is accessed by the system through the st-bus or microprocessor port. the c-channel provides access to two registers which provide complete control over the state activation machine, the d-channel priority mechanism as well as the various maintenance functions. a detailed description of these registers is discussed in the microprocessor port interface.
mt8930c 9-39 figure 5 - s-bus frame structure and functional timing f = framing bit l = dc balancing bit d = bit within d-channel e = d-echo channel bit fa & n (nt to te) = auxiliary framing bits fa (te to nt) = auxiliary framing bit or q-channel bit b1 = bit within b1-channel b2 = bit within b2-channel a = activation bit m = multiframing bit s = s-channel bit b1 b1 b1 b1 b1 b1 e b1 d0 b2 b2 b2 b2 b2 b2 b2 b2 e s d1 l f l b1 b1 fl b1 b1 b1 b1 b1 b1 b1 e d0 a fa n b2 b2 b2 b2 b1 b2 b2 b2 b2 e d1 m b1 b1 b1 b2 l l d1 b1 b1 b1 b1 b1 b1 b1 l d0 l b2 b2 b2 b2 b1 b2 b2 b2 b2 l d1 l b2 l l d1 l fb1 b1 b1 b1 b1 b1 b1 l d0 l fa l b1 b2 b2 b2 b2 b2 b2 b2 fl 62.5 m s 62.5 m s 62.5 m s 62.5 m s b1 b1 b1 nt to te n t x t c t e r v m n t r v m t e x t c te to nt f0b dsti half input nd a f0b dsto half input f0b dsti half nd a f0b dsto half output output note: shaded areas reveal data mapping b1
mt8930c 9-40 line code the line code used on the s-interface is a pseudo ternary code with 100% pulse width as seen in figure 6 below. binary zeros are represented as marks on the line and successive marks will alternate in polarity. figure 6 - alternate zero inversion line code a mark which does not adhere to the alternating polarity is known as a bipolar violation. framing the valid frame structure transmitted by the nt and te contains the following (refer fig. 5): nt to te: - framing bit (f) - b1 and b2 channels (b1,b2) - dc balancing bits (l) - d-channel bits (d0, d1) - auxiliary framing and n bit (fa, n), n= f a - activation bit (a) - d-echo channel bits (e) - multiframing bit (m) - s-channel bit te to nt: - framing bit (f) - b1 and b2 channels (b1, b2) - dc balancing bits (l) - d-channel bits (d0, d1) - auxiliary framing bit (fa) or q-channel bit the framing mechanism on the s-interface makes use of line code violations to identify frame boundaries. the f-bit violates the alternating line code sequence to allow for quick identi?cation of the frame boundaries. to secure the frame alignment, the next mark following the frame balancing bit (l) will also produce a line code violation. if the data following the balancing bit is all binary ones, the zero in the auxiliary framing bit (fa) or n-bit (for the direction nt to te) will provide successive violations to ensure that the 14 bit criterion (13 bit criterion in the direction te to nt) speci?ed in recommendations i.430 and t1.605 is satis?ed. if the b1-channel is not all binary ones, the ?rst zero following the l-bit will violate the line code sequence, thus allowing subsequent marks to alternate without bipolar violations. the fa and n bits can also be used to identify a multiframe structure (when this is done, the 14 bit criterion may not be met). this multiframe structure will make provisions for a low speed signalling channel to be used in the te to nt direction (q-channel). it will consist of a ?ve frame multiframe which can be identi?ed by the binary inversion of the fa and n-bit on the ?rst frame and consequently on every ?fth frame of the multiframe. upon detection of the multiframe signal, the te will replace the next fa- bit to be transmitted with the q-bit. the dc balancing bits (l) are used to remove any dc content from the line. the balancing bit will be a mark if the number of preceding marks up to the previous balancing bit is odd. if the number of marks is even, the l-bit will be a space. the a-bit is used by the nt during line activation procedures (refer to state activation diagrams). the state of the a-bit will advise the te if the nt has achieved synchronization. the e-bit is the d-echo channel. the nt will re?ect the binary value of the received d-channel into the e-bits. this is used to establish the access contention resolution in a point-to-multipoint con?guration. this is described in more detail in the section of the d-channel priority mechanism. the m-bit is a second level of multiframing which is used for structuring the q-bits. the frame with m- bit=1 identi?es frame #1 in the twenty frame multiframe. the q-channel is then received as shown in table 1. all synchronization with the multiframes must be performed externally. table 1. q-channel allocation bit order when using the b-channels for pcm voice, the ?rst bit to be transmitted on the s-bus should be the sign bit. this complies with the existing telecom standards which transmit pcm voice as most signi?cant bit ?rst. however, if the b-channels are to binary value line signal violation 0100010011 frame # q-bit m-bit 1q11 6q20 11 q3 0 16 q4 0
mt8930c 9-41 carry data, the bit ordering must be reversed to comply with the existing datacom standards (i.e., least signi?cant bit ?rst). these contradicting standards place a restriction on all information input and output through the serial and parallel ports. information transferred through the serial ports, will maintain the integrity of the bit order. data sent to either serial port from the parallel port, will transmit the least signi?cant bit ?rst. therefore, a pcm byte input through the microprocessor port must be reordered to have the sign bit as the least signi?cant bit. when the microprocessor reads d, b1 or b2 channel data of either st-bus or s-bus serial port, the least signi?cant bit read is the ?rst bit received on that particular channel of either serial port. the d-channel received on the serial st-bus ports must be ordered with the least signi?cant bit ?rst as shown in figure 4. this also applies to the d-channel directed to the st-bus from the microprocessor port. the c-channel bit mapping from the parallel port to the st-bus is organized such that the most signi?cant bit is transmitted or received ?rst. state activation the state activation controller activates or deactivates the snic in response to line activity or external command. the controller is completely hardware driven and need not be initialized by the microprocessor. the state diagram for initialization is shown in figure 7. the protocol used by the state activation controller is de?ned as follows: 1) in the deactivated state, neither the nt nor te assert a signal on the line (info0). 2) if the te wants to initiate activation, it must begin transmitting a continuous signal consisting of a positive zero, a negative zero followed by six ones (info1). 3) once the nt has detected info1, it begins to transmit info2 which consists of an s-bus frame with zeros in the b and d-channel and the activation bit (a-bit) set to zero. 4) as soon as the te synchronizes to info2, it responds with a valid s-bus frame with data in the b1, b2 and d-channel (info3). 5) the nt will then transmit a valid frame with data in the b1, b2 and d-channel. it will also set the activation bit (a) to binary one once synchronization to info3 is achieved. if the nt wishes to initiate the activation, steps 2 and 3 are ignored and the nt starts sending info2. to initiate a deactivation, either end begins to send info0 (idle line). d-channel priority mechanism the snic contains a hardware priority mechanism for d-channel contention resolution. all tes connected in a point-to-multipoint con?guration are allocated the d-channel using a systematic approach. allocation of the d-channel is accomplished by monitoring the d-echo channel (e-bit) and incrementing the d-channel priority counter with every consecutive one echoed back in the e bit. any zero found on the d-echo channel will reset the priority counter. there are two classes of priority within the snic, one user accessible and the other being strictly internal. the user accessible priority selects the class of operation and has precedence over the internal priority. the latter (internal priority), will select the level of priority within each class (i.e., the internal priority is a subsection of the user accessible priority). user accessible priority selects the terminal count as 8/9 or 10/11 consecutive ones on the e-bit (8 being high priority while 10 being low priority). the internal priority selects the terminal between 8 or 9 for high class and 10 or 11 for low class. the ?rst terminal equipment to attain the e-bit priority count will immediately take control of the d-channel by sending the opening ?ag. if more than one terminal has the same priority, all but one of them will eventually detect a collision. the tes that detect a collision will immediately stop trans-mitting on the d-channel, generate an interrupt through the dcoll bit, reset the dcack bit on the next frame pulse, and restart the counting process. the remainder of the packet in the tx fifo is ignored. after successfully completing a transmission, the internal priority level is reduced from high to low. the internal priority will only be increased once the terminal count for the respective level of priority has been achieved (e.g., if te has high priority internally and externally, it must count 8 consecutive ones in the d-echo channel. once this is achieved and successful transmission has been completed, the internal priority is reduced to a lower level (i.e., count = 9). this terminal will not return to the high internal priority until 9 consecutive ones have been monitored on the d-echo channel).
mt8930c 9-42 figure 7 - link activation protocol, state diagram signals from nt to te signals from te to nt info0 info2 info4 no signal valid frame structure with all b, d, d-echo and a bits set to 0 valid frame with data in b, d, d-echo channels. bit a is set to 1. info1 continuous signal of +0, -0 and six 1s (1) info3 valid frame with data in b & d bits where: ba (2) = bus activity dr = deactivation request ar = activation request sync (2) = frame sync signal a = activation bit time out = 32 ms timer signal note 1: signal is not timebase locked to nt. note 2: sync/ba bit of the status register is configured as sync bit when ar = 1 and dr = 0, or as ba bit when ar = 0 or dr = 1. a change in the state of the ar and/or dr bits will cause a change in the function of the sync/ba bit in the following st-bus frame. te state activ ation dia gram nt state activ ation dia gram dr = 1 ar = 1 sync = 1 ba = 0 sync = 1 dr = 1 dr = 1 ba = 0 a = 1 & sync = 1 sync = 0 a = 0 activation request send info1 if ba = 0 send info0 if ba = 1 deactivated send info0 synchronized send info3 if sync = 1 send info0 if sync = 0 activated send info3 ba = 1 ar = 1 ba =0 time out dr = 1 ar = 1 sync = 1 sync = 0 dr = 1 deactivated send info0 pending activation send info2 pending deactivation send info0 activated send info4 info0 no signal line wiring con?guration the mt8930c can interface to any of the three wiring con?gurations which are speci?ed by ccitt recommendation i.430 and ansi t1.605 (refer to figs. 8 to 10). these consist of a point-to-point or one of the two point-to-multipoint con?gurations (i.e., short passive bus or the extended passive bus). the selection of line con?gurations is performed using the timing bit (b4 of nt mode control register). for the short passive bus, te devices are connected at random points along the cable. however, for the extended passive bus all connection points are grouped at the far end of the cable from the nt. for an nt snic in ?xed timing mode, the vco and rx ?lters/peak detectors are disabled and the threshold voltage is ?xed. however, for a te snic or an nt snic (in adaptive timing mode), the vco and rx ?lters/peak detectors are enabled. in this manner, the device can compensate for variable round trip delays and line attenuation using a threshold voltage set to a ?xed percentage of the pulse peak amplitude. another operation can be implemented using the snic in the star con?guration as shown in figure 14. this mode allows multiple nts, with physically independent s-busses, to share a common input source and transfer information down the s-bus to all
mt8930c 9-43 figure 8 - point-to-point con?guration fiure 9 - short passive bus con?guration, up to 8 tes can be supported figure 10 - extended passive bus con?guration, up to 8 tes can be supported nt te t r t r 0 - 1 km nt is operating in adaptive timing tr is the line termination resistor = 100 w nt te t r t r te te te te te te te 100 m for 75 w impedance cable and 200 m for 150 w impedance cable 100 - 200 m nt is operating in fixed timing tr is the line termination resistor = 100 w 0 - 10 m nt is operating in adaptive timing tr is the line termination resistor = 100 w te te te te te te te 0 - 10 m 0-500 m 0-50 m nt t r t r te tes . all nt devices connected into the star will receive the information transmitted by all tes on all branches of the star, exactly as if they were on the same physical s-bus. all nts in the star con?guration must be operating in ?xed timing mode. refer to the description of the star con?guration in the st-bus section. the snic has one last mode of operation called the nt slave mode. this has the effect of operating the snic in network termination mode (ck/nt pin = 1) but having the frame structure and registers description de?ned by the te mode. this can be used where multiple subscriber loops must carry a ?xed phase relation between each line. a typical situation is when the system is trying to synchronize two nodes of a synchronous network. this allows multiple tes to share a common st-bus timebase. the synchronization of the loops is established by using the clock signals produced by a local te as an input timing source to the nt slave. adaptive timing operation on power-up or after a reset, the snic in nt mode is set to operate in ?xed timing. to switch to adaptive timing, the user should: 1) set the dr bit to 1 2) set the timing bit to 1 in the c-channel control register 3) wait for 100 ms period 4) proceed in using the ar and dr bits as desired switching from adaptive timing mode is completed by resetting the timing bit.
mt8930c 9-44 figure 11 - st-bus stream format figure 12 - clock & frame alignment for st-bus streams channel 0 channel 1 channel 2 channel 30 channel 31 channel 0 ??? bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (8/2048) ms 125 m s f0b c4b st-bus bit cells channel 31 bit 0 channel 0 bit 7 channel 0 bit 6 channel 0 bit 5 channel 0 bit 4 st-bus interface the st-bus is a synchronous time division multiplexed serial bussing scheme with data streams operating at 2048 kbit/s con?gured as 32, 64 kbit/s channels (refer to fig. 11). synchronization of the data transfer is provided from a frame pulse which identi?es the frame boundaries and repeats at an 8 khz rate. figure 4 shows how the frame pulse ( f0b) de?nes the st-bus frame boundaries. all data is clocked into the device on the rising edge of the 4096 khz clock ( c4b) three quarters of the way into the bit cell, while data is clocked out on the falling edge of the 4096 khz clock at the start of the bit cell. all timing signals (i.e. f0b & c4b) are identi?ed as bidirectional (denoted by the terminating b). the i/o con?guration of these pins is controlled by the mode of operation (nt or te). in the nt mode, all synchronized signals are supplied from an external source and the snic uses this timing while transferring information to and from the s or st-bus. in the te mode, an on-board analog phase-locked loop extracts timing from the received data on the s-bus and generates the system 4096 khz ( c4b) and frame pulse ( f0b). the analog phase-locked loop also maintains proper phase relation between the timing signals as well as ?ltering out jitter which may be present on the received line port. when the te mode is selected by tying the ck/nt pin low, a continuous info0 signal on the receiver will cause the pll frequency to drift from its nominal 4.096 mhz value ( c4b output). hence, transmitted info1 from the te will not be at 192 kbps as required in i.430 and t1.605. however, if the users application requires the transmission of info1 at exactly 192 kbit/s or the presence of an exact 4.096 mhz c4b clock at all times, then a 4.096 mhz clock should be connected to the ck/nt pin. this input clock serves to con?gure the device in te mode and to train the pll in the absence of an info2 or info4 signal on the line. the snic uses the ?rst four channels on the st-bus (as shown in figure 4). to simplify the distribution of the serial stream, the snic provides a delayed frame pulse ( f0od) to eliminate the need for a channel assignment circuit. this signal is used to drive subsequent devices in the daisy chain (refer figure 13). in this type of arrangement, only the ?rst snic in the chain will receive the system frame pulse ( f0b) with the following devices receiving its predecessors delayed output frame pulse ( f0od). the snic makes ef?cient use of its tdm bus through the star con?guration. it does so by sharing four common st-bus channels to multiple nt devices.
mt8930c 9-45 figure 13 - daisy chaining the snic figure 14 - nt in star con?guration st-bus clock st-bus stream system frame pulse mt8930c nt f0b f0od mt8930c nt f0b f0od mt8930c nt f0b f0od mt8930c nt f0b f0od to te to te to te to te active on channel 0 - 3 active on channels 4 - 7 active on channels 8 - 11 active on channels 12 - 15 v dd to te to te star f0b dsti star f0b dsti mt8930c nt mt8930c nt mt8930c nt mt8930c nt to te to te system frame pulse input st-bus stream output st-bus stream star f0b dsti star f0b dsti dsto up to eight snics in nt mode with physically independent s-busses can be connected in parallel to realize a star con?guration, as shown in figure 14. all devices connected into the star will carry the same input, thus information is sent to all tes simultaneously. the 2b+d data received from every te is transmitted to all nts through the star pin. consequently, all the dsto streams will carry identical 2b+d data re?ecting what is being transmitted by the various tes. the ?ow of data in the direction of s-bus to st-bus is transparent to the snic, regardless of the state machine status. on the other hand, the ?ow of data in the direction of st-bus to s-bus becomes transparent only after the state machine is in the active state (is0, is1=1,1), in case of an nt, or in the synchronization state (is0, is1=1), in case of a te. microprocessor/control interface the parallel port on the snic operates as either a general purpose microprocessor interface or as a hardwired control port. in microprocessor control mode (cmode = 1), the parallel port is compatible with either motorola or intel multiplexed bus signals and timing. the motel circuit ( mo torola and in tel compatible bus) uses the level of the ds/ rd pin at the rising edge of as/ale to select the appropriate bus timing. if ds/ rd is low at the rising edge of as/ale (refer fig. 26) then motorola bus timing is selected. conversely, if ds/ rd is high at the rising edge of as/ale (refer figs. 24 & 25), then intel bus timing is selected. this has the effect of rede?ning the microprocessor port transparently to the user. in this mode, the user has the option of writing to the c-channel control or diagnostic register through the parallel port interface or through the c-channel on dsti. bit 0 of the master control register provides this option. the parallel port on the snic allows complete control of the hdlc transceiver and access to all data, control and status registers. the internal registers (de?ned in table 2) can be accessed through the microprocessor port only when the cmode pin is held high. reading these registers allows the microprocessor to monitor incoming data on the s or st-bus without interrupting the normal data ?ow.
mt8930c 9-46 table 2. snic address map address lines write read a4 a3 a2 a1 a0 0 0 0 0 0 master control register verify a 0 0 0 0 1 st-bus control register verify s 0 0 0 1 0 hdlc control register 1 verify y 0 0 0 1 1 hdlc control register 2 hdlc status register n 0 0 1 0 0 hdlc interrupt mask register hdlc interrupt status register c 0 0 1 0 1 hdlc tx fifo hdlc rx fifo 0 0 1 1 0 hdlc address byte #1 register verify 0 0 1 1 1 hdlc address byte #2 register verify 0 1 0 0 0 c-channel control register 0 1 0 0 1 c-channel status register 1 0 0 0 0 control register 1 not available 1 0 0 1 0 not available master status register 0 1 0 0 0 dsti c-channel 0 1 0 0 1 dsto c-channel s 0 1 0 1 0 s-bus tx d-channel dsti d-channel y 0 1 0 1 1 dsto d-channel s-bus rx d-channel n 0 1 1 0 0 s-bus tx b1-channel dsti b1-channel c 0 1 1 0 1 dsto b1-channel s-bus rx b1-channel 0 1 1 1 0 s-bus tx b2-channel dsti b2-channel 0 1 1 1 1 dsto b2-channel s-bus rx b2-channel some registers are classi?ed as asynchronous and others as synchronous. synchronous registers are single-buffered and require synchronous access. not all the synchronous registers have the same access times, but all can be accessed synchronously in the time during which the nd a signal is low (refer to fig. 5). therefore, it is recommended that the user make use of the nd a signal to access these registers. since the synchronous registers use common circuitry, it is essential that the register be read before being written. this sequence is important as a write cycle will overwrite the last data received. these parallel accesses must be refreshed every frame. asynchronous registers, on the other hand, can be accessed at any time. when the cmode pin is low, controllerless mode is selected and the parallel port reverts to hardwired control/status pins. this allows the mt8930c to function without the need for a controlling microprocessor. in the controllerless mode, the parallel bus has direct connection to the relevant control/status registers (refer to pin description). discrete logic can be used to drive/sense the respective pins. in this mode, pin 11 (p/ sc determines whether the microport pins or the c-channel bits on dsti stream are the control source of the device. if the c-channel is selected to be the source, p/ sc is tied low, then the microport pins are ignored and the c-channel is loaded into the c-channel control register. the data in te or nt mode status register, depending upon the mode selected, is always sent out on the c-channel of dsto. however, in microprocessor control mode the user can overwrite this data by writing to the dsto c-channel register. this access can be done anytime outside the frame pulse interval of the st-bus frame. data written in the current st-bus frame will only appear in the c- channel of the following frame. the least signi?cant bit (b0) of the c-channel register, selects between the control register or the diagnostic register. setting the b0 of the c-channel register to 0 allow access to the control register. setting the lsb of the c-channel register to 1 allow access to the diagnostic register. the interpretation of each register is de?ned in tables 13 and 14 for nt mode or tables 16 and 17 for the te mode. it is important to note that in te mode, the c-channel diagnostic register should be cleared while the device is not in the active state (is0, is1 1 1,1). this is accomplished by setting the clrdia bit of the c- channel control register to 1 until the device is activated. in serial control mode, the c-channel on the st-bus is loaded into the c-channel control register in every st-bus frame; the user should make sure that a 1 is written to the clrdia bit in every frame. however, in parallel control mode the user needs to set the clrdia bit only once to keep the
mt8930c 9-47 diagnostic register cleared. once full activation is achieved the diagnostic register can be written to in order to enable the various test functions. hdlc transceiver the hdlc transceiver handles the bit oriented protocol structure and formats the d-channel as per level 2 of the x.25 packet switching protocol de?ned by ccitt. it transmits and receives the packetized data (information or control) serially in a format shown in figure 15, while providing data transparency by zero insertion and deletion. it generates and detects the ?ags, various link channel states and the abort sequence. further, it provides a cyclic redundancy check on the data packets using the ccitt de?ned polynomial. in addition, it can recognize a single byte, dual byte or an all call address in the received frame. there is also a provision to disable the protocol functions and provide transparent access to either serial port through the microprocessor port. other features provided by the hdlc include, independent port selection for transmit and received data (e.g. transmit on s-bus and receive from st-bus), selectable 16 or 64 kbit/s d-channel as well as an hdlc loopback from the transmit to the receive port. these features are enabled through the hdlc control registers (see tables 6 and 7). hdlc frame format all frames start with an opening ?ag and end with a closing ?ag as shown in figure 15. between these two ?ags, a frame contains the data and the frame check sequence (fcs). figure 15 - frame format i) flag the ?ag is a unique pattern of 8 bits (01111110) de?ning the frame boundary. the transmit section generates the ?ags and appends them automatically to the frame to be transmitted. the receive section searches the incoming packets for ?ags on a bit-by-bit basis and establishes frame synchronization. the ?ags are used only to identify and synchronize the received frame and are not transferred to the fifo. ii) data the data ?eld refers to the address, control and information ?elds de?ned in the ccitt recommendations. a valid frame should have a data ?eld of at least 16 bits. the ?rst and second byte in the data ?eld is the address of the frame. iii) frame check sequence (fcs) the 16 bits following the data ?eld are the frame check sequence bits. the generator polynomial is: g(x)=x 16 +x 12 +x 5 +1 the transmitter calculates the fcs on all bits of the data ?eld and transmits the complement of the fcs with most signi?cant bit ?rst. the receiver performs a similar computation on all bits of the received data but also includes the fcs ?eld. the generating polynomial will assure that if the integrity of of the transmitted data was maintained, the remainder will have a consistent pattern and this can be used to identify, with high probability, any bit errors occurred during transmission. the error status of the received packet is indicated by b7 and b6 bits in the hdlc status register. iv) zero insertion and deletion the transmitter, while sending either data from the fifo or the 16 bits fcs, checks the transmission on a bit-by-bit basis and inserts a zero after every sequence of ?ve contiguous ones (including the last ?ve bits of fcs) to ensure that the ?ag sequence is not imitated. similarly the receiver examines the incoming frame content and discards any zero directly following the ?ve contiguous ones. v) abort the transmitter aborts a frame by sending a zero followed by seven consecutive ones. the fa bit in the hdlc control register 2 along with a write to the hdlc transmit fifo enables the transmission of an abort sequence instead of the byte written to the register (to have a valid abort there must be at least two bytes in the packet). on the receive side, a frame abort is de?ned as seven or more contiguous ones occurring after the start ?ag and before the end ?ag of a packet. an interrupt can be generated on reception of the abort sequence using fa bit in the hdlc interrupt mask/vector registers (refer to tables 9 and 10). flag data field fcs flag one byte n bytes (n 3 2) tw o bytes one byte
mt8930c 9-48 interframe time fill when the hdlc tranceiver is not sending packets, the transmitter can be in one of two states mentioned below depending on the status of the iftf bit in the hdlc control register 1. i) idle state the idle state is de?ned as 15 or more contiguous ones. when the hdlc protocoller is observing this condition on the receiving channel, the idle bit in the hdlc status register is set high. on the transmit side, the protocoller ends the transmission of all ones (idle state) when data is loaded into the transmit fifo. ccitt i.430 speci?cation requires every te that does not have layer 2 frames to transmit, to send binary ones on the d-channel. in this manner, other tes on the line will have the opportunity to access the d-channel using the priority mechanism circuitry. ii) flag fill state the hdlc protocoller transmits continuous ?ags (7e hex ) in interframe time fill state and ends this state when data is loaded into the transmit fifo. the reception of the interframe time ?ll will have the effect of setting the idle bit in the hdlc status register is set to 0. hdlc transmitter on power up, the hdlc transmitter is disabled and in the idle state. the transmitter is enabled by setting the txen bit in the hdlc control register 1. to start a packet, the data is written into the 19 byte transmit fifo starting with the address ?eld. all the data must be written to the fifo in a bytewide manner. when the data is detected in the transmit fifo, the hdlc protocoller will proceed in one of the following ways: 1) if the transmitter is in idle state, the present byte of ones is completely transmitted before sending the opening ?ag. the data in the transmit fifo is then transmitted. a te transmitting on the d- channel will use the contention circuitry described previously in d-channel priority mechanism to access this channel. 2) if the transmitter is in the ?ag ?ll state, the ?ag presently being transmitted is used as the opening ?ag for the packet stored in the transmit fifo. 3) if the hdlc transmitter is in transparent data mode, the protocol functions are disabled and the data in the transmit fifo is transmitted without a framing structure. to indicate that the particular byte is the last byte of the packet, the eop bit in the hdlc control register 2 must be set before the last byte is written into the transmit fifo. the eop bit is cleared automatically when the data byte is written to the fifo. after the transmission of the last byte in the packet, the frame check sequence (16 bits) is sent followed by a closing ?ag. if there is any more data in the transmit fifo, it is immediately sent after the closing ?ag. that is, the closing ?ag of a packet is also used as the opening ?ag the the next packet. however, ccitt i.430 and ansi t1.605 recommendations state that after the successful transmission of a packet, a te must lower its priority level within the speci?ed priority class. the user can meet this requirement by loading the tx fifo with no more than one packet and then waiting for the dcack bit to go to zero, or for an hdlc interrupt by the teop bit in the hdlc interrupt status register, before attempting to load a new packet. if there is no more data to be transmitted, the transmitter assumes the selected link channel state. during the transmission of either the data or the frame check sequence, the protocol controller checks the transmitted information on a bit by bit basis to insert a zero after every sequence of ?ve consecutive ones. this is required to eliminate the possibility of imitating the opening or closing ?ag, the idle code or an abort sequence. i) transmit underrun a transmit underrun occurs when the last byte loaded into the transmit fifo was not ?agged with the end of packet (eop) bit and there are no more bytes in the fifo. in such a situation, the protocol controller transmits the abort sequence (zero and seven ones) and moves to the selected link channel state. conversely, in the event that the transmit fifo is full, any further writes will overwrite the last byte in the transmit fifo. ii) abort transmission if it is desired to abort the packet currently being loaded into the transmit fifo, the next byte written to the fifo should be ?agged to cause this to happen. the fa bit of the hdlc control register 2 must be
mt8930c 9-49 set high, before writing the next byte into the fifo. this bit is cleared automatically once the byte is written to the transmit fifo. when the ?agged byte reaches the bottom of the fifo, a frame abort sequence is sent instead of the byte and the transmitter operation returns to normal. the frame abort sequence is ignored if the packet has less then two bytes. iii) transparent data transfer the trans bit (b4) in the hdlc control register 2 can be set to provide transparent data transfer by disabling the protocol functions. the transmitter no longer generates the flag, abort and idle sequences nor does it insert the zeros and calculate the fcs. it should be noted that none of the protocol related status or interrupt bits are applicable in transparent data transfer state. however, the fifo related status and interrupt bits are pertinent and carry the same meaning as they do while performing the protocol functions. hdlc receiver after a reset on power up, the receive section is disabled. address detection is also disabled when a reset occurs. if address detection is required, the receiver address registers are loaded with the desired address and the adrec bit in the hdlc control register 1 is set high. the receive section can then be enabled by rxen bit in this same control register 1. all hdlc interrupts are masked, thus the desired interrupt signal must be unmasked through the hdlc interrupt mask register. all active interrupts are cleared by reading the hdlc interrupt status register. i) normal packets after initialization as explained above, the serial data starts to be clocked in and the receiver checks for the idle channel and ?ags. if an idle channel is detected, the idle bit in the hdlc status register is set high. once a ?ag is detected, the receiver synchronizes itself in a bytewide manner to the incoming data stream. the receiver keeps resynchronizing to the ?ags until an incoming packet appears. the incoming packet is examined on a bit-by-bit basis, inserted zeros are deleted, the fcs is calculated and the data bytes are written into the 19 byte receive fifo. however, the fcs and other control characters, i.e., ?ag and abort , are never stored in the receive fifo. if the address detection is enabled, the address ?eld following the ?ag is compared to the bytes in the receive address registers. if one byte address recognition is enabled, the address ?eld is one byte long and it is compared with the six most signi?cant bits in address recognition register 1. if two byte address recognition is enabled, the address ?eld is two bytes long and is compared with the address recognition registers 1 and 2. the address byte can also be recognized if it is an all call address (i.e., seven most signi?cant bits are 1). if a match is not found, the entire packet is ignored, nothing is written to the receive fifo and the receiver waits for the next packet. if the active address byte is valid, the packet is received in normal fashion. all the bytes written to the receive fifo are ?agged with two status bits. the status bits are found in the hdlc status register and indicate whether the byte to be read from the fifo is the ?rst byte of the packet, the middle of the packet, the last byte of the packet with good fcs or the last byte of the packet with bad fcs. this status indication is valid for the byte which is to be read from the receive fifo. the incoming data is always written to the fifo in a bytewide manner. however, in the event of data sent not being a multiple of eight bits, the software associated with the receiver should be able to pick the data bits from the lsb positions of the last byte in the received data written to the fifo. the protocoller does not provide any indication as to how many bits this might be. ii) invalid packets in te mode, if there are less than 25 data bits between the opening and closing ?ags, the packet is considered invalid and the data never enters the receive fifo (inserted zeros do not form part of the valid bit count). this is true even with data and the abort sequence, the total of which is less than 25 bits. the data packets that are at least 25 bits but less than 32 bits long are also invalid, but not ignored. they are clocked into the receive fifo and tagged as having bad fcs. in nt mode, however, all the data packets that are less than 32 bits long are considered invalid. they are clocked into the receive fifo with bad fcs status. iii) frame abort when a frame abort is received, the eopd and fa bits in the hdlc interrupt status register are set. the last byte of the aborted packet is written to the fifo with a status of packet byte. if there is more than one packet in the fifo, the aborted packet is
mt8930c 9-50 distinguished by the fact that it has no last byte status on any of its bytes. iv) idle channel while receiving the idle channel, the idle bit in the hdlc status register remains set. v) transparent data transfer by setting the trans bit in the hdlc control register 2 to select the transparent data transfer, the receive section will disable the protocol functions like flag/ abort/idle detection, zero deletion, crc calculation and address comparison. the received data is shifted in from the active port and written to receive fifo in bytewide format. it should be noted that none of the protocol related status or interrupt bits are applicable in transparent data transfer state. however, the fifo related status and interrupt bits are pertinent and carry the same meaning as they do while performing the protocol functions. vi) receive over?ow receive over?ow occurs when the receive section attempts to load a byte to an already full receive fifo. all attempts to write to the full fifo will be ignored until the receive fifo is read. when over?ow occurs, the rest of the present packet is ignored as the receiver will be disabled until the reception of the next opening ?ag. table 3. master control register (read/write add. 00000 b ) note 1: these bits have no designated memory space and will read as the last values written to the microprocessor port. note 2: the transmission of m=1 is used for a second level of multiframing. table 4. control register 1 (write add. 10000 b ) bit name description b7 na a 1 will allow access to control register 1 and master status register. a 0 will prevent it. b6-b3 na (1) keep at 0 for normal operation. b2 irq/ nd a the state of this pin will select the mode of the irq/ nd a pin. a 0 will enable the irq pin for hdlc interrupts. a 1 will enable the new data available signal which identi?es the access time to the synchronous registers. (if nd a is enabled, the hdlc interrupts are disabled.) b1 m/ sen a 0 will enable the transmission of the m (2) or s bit as selected in the nt mode c-channel register (refer to table 13). the selection of m or s is determined by the half signal (refer to functional timing). a 1 will disable this feature forcing the m and s bits to binary zero. b0 p/ sc the parallel/serial control bit selects the source of the control channel. if 0, then the c- channel register is access through the st-bus stream. if 1, then the c-channel register is accessed through the microprocessor port. bit name description b7 na keep at 0 for normal operation. b6 rxdis when set to 1, this bit disables the s-bus signal receiver. it can be used, for example, to force info4 to info2 transition in the nt state machine while receiving info3 from the te. b5-b0 na keep at 0 for normal operation.
mt8930c 9-51 table 5. st-bus control register (read/write add. 00001 b ) note 3: all st-bus channels are enabled in controllerless mode. table 6. hdlc control register 1 (read/write add. 00010 b ) note 1: the hdlc receiver must be enabled as well as the designated channel. bit name description b7 ch3i (3) if 1, then the st-bus channel 3 input port is enabled (b2-channel). if 0, then the channel is disabled, and will read ff h . b6 ch2i (3) if 1, then the st-bus channel 2 input port is enabled (b1-channel). if 0, then the channel is disabled, and will read ff h . b5 ch1i (3) if 1, then the st-bus channel 1 input port is enabled (c-channel). if 0, then the channel is disabled, and will read 00 h . b4 ch0i (3) if 1, then the st-bus channel 0 input port is enabled (d-channel). if 0, then the channel is disabled, and will read ff h . b3 ch3o (3) if 1, then the st-bus channel 3 output port is enabled (b2-channel). if 0, then the channel is disabled and it will be placed in high impedance. b2 ch2o (3) if 1, then the st-bus channel 2 output port is enabled (b1-channel). if 0, then the channel is disabled and it will be placed in high impedance. b1 ch1o (3) if 1, then the st-bus channel 1 output port is enabled (c-channel). if 0, then the channel is disabled and it will be placed in high impedance b0 ch0o (3) if 1, then the st-bus channel 0 output port is enabled (d-channel). if 0, then the channel is disabled and it will be placed in high impedance. bit name description b7 txen a 1 enables the hdlc transmitter for the selected d-channel (i.e., st-bus or s-bus). a 0 disables the hdlc transmitter (i.e., an all 1s signal will be sent). b6 rxen a 1 enables the hdlc receiver for the selected d-channel (i.e., st-bus or s-bus). a 0 disables the hdlc receiver (i.e., an all 1s signal will be received). b5 adrec if 1, then the address recognition is enabled. this forces the receiver to recognize only those packets having the unique address as programmed in the receive address registers or if the address byte is the all-call address (all 1s). if 0, then the address recognition is disabled and every valid packet is stored in the received fifo. b4 txprtsel this bit selects the port of the hdlc transmitted d-channel. a1 selects the s-bus port. a 0 selects the st-bus port. b3 rxprtsel this bit selects the port of the hdlc received d-channel. a 1 selects the s-bus port. a 0 selects the st-bus port. b2 iftf this bit selects the inter frame time fill. a 1 selects continuous ?ags. a 0 selects an all 1s idle state. b1 na keep at 0 for normal operation. b0 hloop a 1 will activate the hdlc loopback where the transmitted d-channel is looped back to the received d-channel (1) . in nt mode, the transmission of the packet is not affected. in te mode, however, the dreq bit of c-channel control register must be set to 1 for the packet to be transmitted to the s-bus. a 0 disables the loopback.
mt8930c 9-52 table 7. hdlc control register 2 (write add. 00011 b ) note 2: these bits will be reset after a write to the txfifo table 8. hdlc status register (read add. 00011 b ) bit name description b7-b5 na keep at 0 for normal operation. b4 trans a 1 will place the hdlc in a transparent mode. this will perform the serial to parallel or parallel to serial conversion without inserting or deleting the opening and closing ?ags, crc bytes or zero insertion. the source or destination of the data is determined by the port selection bits in the hdlc control register 1. b3 rxrst a transition from 0 to 1 will reset the receive fifo. this causes the receiver to be disabled until the reception of the next ?ag. (the status register will identify the rxfifo as being empty). the device resets this bit to 0 immediately after clearing the receive fifo. b2 txrst a transition from 0 to 1 will reset the transmit fifo. this causes the transmitter to clear all data in the txfifo. the device resets this bit to 0 immediately after clearing the transmit fifo. b1 fa (2) a 1 will tag the next byte written to the transmit fifo and cause an abort sequence to be transmitted once it reaches the bottom of the fifo. b0 eop (2) a 1 will tag the next byte written to the transmit fifo and cause an end of packet sequence to be transmitted once it reaches the bottom of the fifo. bit name description b7-b6 rxbyte status these two bits indicate the status of the received byte which is ready to be read from the 19 deep received fifo. the status is encoded as follows: b7 -b6 0 - 0 - packet byte 0 - 1 - first byte 1 - 0 - last byte (good fcs) 1 - 1 - last byte (bad fcs) b5-b4 rxfifo status these two bits indicate the status of the 19 deep receive fifo. this status is encoded as follows: b5 - b4 0 - 0 - rx fifo empty 0 - 0 - 14 bytes 1 - 0 - rx fifo over?ow 1 - 1 - 3 15 bytes b3-b2 txfifo status these two bits indicate the status of the 19 deep transmit fifo as follows: b3 - b2 0 - 0 - tx fifo full 0 - 1 - 3 5 bytes 1 - 0 - tx fifo empty 1 - 1 - bytes b1 idle if 1, an idle channel state has been detected. b0 int if 1 an unmasked asynchronous interrupt has been detected.
mt8930c 9-53 table 9. hdlc interrupt mask register (write add. 00100 b ) table 10. hdlc interrupt status register (read add. 00100 b ) note 1: all interrupts will be reset after a read to the hdlc interrupt status register. bit name description b7 endcoll a 1 will enable the d-channel collision interrupt. a 0 will disable it. this bit is available only in te mode. b6 eneopd a 1 will enable the received end of packet interrupt. a 0 will disable it. b5 enteop a 1 will enable the transmit end of packet interrupt. a 0 will disable it. b4 enfa a 1 will enable the frame abort interrupt. a 0 will disable it. b3 entxfl a 1 will enable the transmit fifo low interrupt. a 0 will disable it. b2 entxfun a 1 will enable the transmit fifo underrun interrupt. a 0 will disable it. b1 enrxff a 1 will enable the receive fifo full interrupt. a 0 will disable it. b0 enrxfov a 1 will enable the receive fifo over?ow interrupt. a 0 will disable it. bit name description b7 dcoll (1) a 1 indicates that a collision has been detected on the d-channel (i.e., received e-bit does not match with transmitted d-bit). this bit is available only in te mode and when the hdlc transmitter is enabled. it always reads 0 in nt mode. b6 eopd (1) a 1indicates that an end of packet has been detected on the hdlc receiver. this can be in the form of a ?ag, an abort sequence or as an invalid packet. b5 teop (1) a 1 indicates that the transmitter has ?nished sending the closing ?ag of the last packet in the tx fifo, and the internal priority level is reduced from high to low. b4 fa (1) a 1 indicates that the receiver has detected a frame abort sequence on the received data stream. b3 txfl (1) a 1 indicates that the device has only four bytes remaining in the tx fifo. this bit has signi?cance only when the tx fifo is being depleted and not when it is getting loaded. b2 txfun (1) a 1 indicates that the tx fifo is empty without being given the end of packet indication. the hdlc will transmit an abort sequence after encountering an underrun condition. b1 rxff (1) a 1 indicates that the hdlc controller has accumulated at least 15 bytes in the rx fifo. b0 rxfov (1) a 1 indicates that the rx fifo has over?own (i.e., an attempt to write to a full rx fifo). the hdlc will always disable the receiver once the receive over?ow has been detected. the receiver will be re-enabled upon detection of the next ?ag.
mt8930c 9-54 table 11. hdlc address recognition register 1 (read/write add. 00110 b ) table 12. hdlc address recognition register 2 (read/write add. 00111 b ) table 13. nt mode c-channel control register (2) (write add. 01000 b and b0 = 0) note 1: allow one st-bus frame to input the c-channel and one st-bus frame to establish the connection. note 2: the c-channel control register is updated once every st-bus frame. therefore, this register should not be written to more than once per frame, otherwise, the last access will override previous ones. bit name description b7-b2 r1a7-r1a2 a six bit mask used to interrogate the ?rst byte of the received address (where b7 is msb). if address recognition is enabled, any packet failing the address comparison will not be stored in the rx fifo. b1 na not applicable to address recognition. b0 a1en if 0, the ?rst byte of the address ?eld will not be used during address recognition. if 1 and the address recognition is enabled, the six most signi?cant bits of the ?rst address byte will be compared with the ?rst six bits of this register. bit name description b7-b1 r2a7-r2a1 a seven bit mask used to interrogate the second byte of the received address (where b7 is msb). if address recognition is enabled, any packet failing the address comparison will not be stored in the rx fifo. this mask is ignored if the address is a broadcast (i.e., r2a = 1111111). b0 a2en if 0, the second byte of the address ?eld will not be used during address recognition. if 1 and the address recognition is enabled, the seven most signi?cant bits of the second address byte will be compared with the ?rst seven bits of this register. bit name description b7 ar setting this bit will initiate the activation of the s-bus. if 0, the device will remain in the present state. b6 dr setting this bit will initiate the deactivation of the s-bus. if 0, the device will remain in the present state. this bit has priority over ar. b5 dinb if 1, the d-channel will be placed in the b1 timeslot allocating 64 kbit/s to the d-channel. (1) if 0, the d-channel will assume its position with a 16 kbit/s bandwidth. (1) b4 timing a 0 will set the nt in a short passive bus con?guration using a ?xed timing source (no compensation for line length). a 1 will set the nt in a point-to-point or extended passive bus con?guration with adaptive timing compensation. b3 m/s this bit represents the state of the transmitted m/s-bit. m when half=0 and s when half=1. b2 half the state of this bit identi?es which half of the frame will be transmitted on the s- bus. the operation of this signal is similar to that of the half pin. b1 txmfr a 1 in this bit, while half = 0, will force the transmission of a multiframe sequence in the fa and n bits, i.e., fa=1 and n=0. a 0 will resume normal operation, i.e., fa=0 and n=1. b0 regsel if the register select bit is set to 1, the control register is rede?ned as the diagnostic register. a 0 give access to the control register.
mt8930c 9-55 table 14. nt mode c-channel diagnostic register (write add. 01000 b and b0 = 1) table 15. nt mode status register (2) (read add. 01001 b ) note 1: bus activity is set when three zeros are received in a time period equivalent to 48 bits or 250 m s. it is reset when 128 consecutive ones are received. note 2: the status register is updated internally once every st-bus frame. therefore, more than one read access per frame will return the same value. bit name description b7-b6 loop the status of these two bits determine which type of loopback is to be performed: b7 - b6 0 - 0 - no loopback active 0 - 1 - near end loopback ltx to lrx 1 - 0 - digital loopback dsti to dsto 1 - 1 - remote loopback lrx to ltx b5 fsync if 1, the device will maintain frame synchronization even after losing the framing sequence (i.e., if the device is transmitting info2 or info4 and this bit is set, the same info signal will still be transmitted even if the frame sync sequence in the received signal is lost). if 0, synchronization will be declared when three consecutive framing sequences have been detected without error. b4 flv if 1, the frame sync sequence will violate the bipolar violation encoding rule. if 0, the framing pattern resumes normal operation, i.e., framing bit is a bipolar violation. b3 idle setting this bit to 1 will force an all 1s signal to be transmitted on the line. b2 echo setting this bit to 1 will force all d-echo bits (e) to zero. b1 slave if 1, the device will operate in a nt slave mode. this allows the device to be used at the terminal equipment end of the line while receiving its clocks from an external source. b0 regsel if the register select bit is set to 1, the control register is rede?ned as the diagnostic register. a 0 gives access to the control register. bit name description b7 sync/ba this bit is set when the device has achieved frame synchronization while the activation request is asserted (dr = 0 and ar = 1). if there is a deactivation request or ar is low (dr = 1 or ar = 0), this bit indicates the presence of bus activity (1) . a bus activity identi?es the reception of info frames (info1 or info3). b6-b5 is0-is1 binary encoded state sequence. is0 - is1 0 - 0 - deactivated 0 - 1 - pending deactivation 1 - 0 - pending activation 1 - 1 - activated b4 rxmch following a 0 input at the half pin or half bit in the c-channel control register, the state of this bit re?ects the received maintenance q-channel (received in the fa bit position during multiframing). this bit will always read 1 if multiframing is not used. b3-b0 na these bits will read 1.
mt8930c 9-56 table 16. te mode c-channel control register (2) (write add. 01000 b and b0 = 0) note 1: allow one st-bus frame to input the c-channel and one st-bus frame to establish the connection. note 2: the c-channel control register is updated once every st-bus frame. therefore, this register should not be written to more than once per frame, otherwise, the last access will override previous ones. table 17. te mode diagnostic register (write add. 01000 b and b0 = 1) bit name description b7 ar setting this bit will initiate the activation of the s-bus. if 0, the device will remain in the present state. b6 dr setting this bit will initiate the deactivation of the s-bus. if 0, the device will remain in the present state. this bit has priority over ar. b5 dinb if 1, the d-channel will be placed in the b1 timeslot allocating 64 kbit/s to the d-channel. (1) if 0, the d-channel will assume its position with a 16 kbit/s bandwidth. (1) b4 priority the status of this bit selects the priority class of the terminal equipment. a 1 selects the high priority and a 0 selects the low priority. b3 dreq this bit is used to request or relinquish the d-channel on the s-bus when the d-channel source is the st-bus. a 1 will request the d-channel, a 0 will relinquish it. keep at 0 when the d-channel source is the hdlc transmitter. b2 txmch the state of this bit will be transmitted in the maintenance channel (q-channel). b1 clrdia a 1 will clear the contents of the diagnostics register. a 0 will enable the maintenance functions found in the diagnostic register. this bit should be set to 1 as long as the device is not fully active (is0, is1 1 1,1). b0 regsel if the register select bit is set to 1, the control register is rede?ned as the diagnostic register. a 0 gives access to the control register. bit name description b7-b6 loop the status of these two bits determine which type of loopback is to be performed: b7 - b6 0 - 0 - no loopback active 0 - 1 - near end loopback ltx to lrx 1 - 0 - digital loopback dsti to dsto 1 - 1 - remote loopback lrx to ltx b5 fsync if 1, the device will maintain frame synchronization even after losing the frame sync sequence (i.e., if the device is transmitting info3 and this bit is set, info3 will still be transmitted even if the frame sync sequence in the received signal is lost). if 0, synchronization will be declared when three consecutive framing sequences have been detected. b4 flv if 1, the frame sync sequence will violate the normal bipolar encoding rule. if 0, the framing pattern resumes normal operation, i.e., framing bit will be a bipolar violation. b3 idle if 1, an all 1s signal is transmitted on the line. if 0, the transmitter will resume normal operation. b2-b1 na unused. b0 regsel if the register select bit is set to 1, the control register is rede?ned as the diagnostic register. a 0 gives access to the control register.
mt8930c 9-57 table 18. te mode status register (2) (read add. 01001 b ) note 1: bus activity is set when three zeros are received in a time period equivalent to 48 bits or 250 m s. it is reset when 128 consecutive ones are received. note 2: the status register is updated internally once every st-bus frame. therefore, more than one read access per frame will return the same value. table 19. master status register (read add. 10010 b ) * these two bits can be used along with status bits is0 and is1 to distinguish between states f6/f8 and f4/f5 of the devices state machine in te mode. please refer to state machine section of application note msan-141 for further details. bit name description b7 sync/ba this bit is set if the device has achieved frame synchronization while the activation request is asserted (dr = 0 and ar = 1). if there is a deactivation request or that ar is low ( dr = 1 or ar = 0), this pin indicates the presence of bus activity (1) . a bus activity identi?es the reception of info frames (info2 or info4). b6-b5 is0-is1 binary encoded state sequence. is0 - is1 0 - 0 - deactivated 0 - 1 - synchronized 1 - 0 - activation request 1 - 1 - activated b4 m/s this bit respresents the state of the received m/s-bit. m when half=0 and s when half=1 b3 half the state of this bit identi?es which half of the s-bus frame is currently being output on the st-bus. b2 rxmfr a 1 when half=0 indicates that the multiframe pattern on fa and n has been detected. b1 priority the status of this bit indicates the internal priority of the device within the designated priority class. if 1, then it has high priority within the priority class designated in b4 of control register. if 0, then it has low priority within the priority class designated in b4 of control register. b0 dcack a 1 indicates that the device has gained access to the d-channel and has transmitted an opening ?ag. this bit is reset to 0 when the closing ?ag of the last packet in the txfifo is transmitted and the internal priority is reduced from high to low. a collision during transmission will also reset this bit back to 0. bit name description b7-b2 na not available. b1* info1 in te mode, this bit is set to 1 only when the device is transmitting info1. not available in nt mode. b0* info0 in nt or te mode, this bit is set to 1 only when the device is transmitting info0.
mt8930c 9-58 applications the mt8930c is useful in a wide variety of isdn applications. being used at both the network termination (nt) and terminal equipment (te) ends of the line, the snic ?nds application on digital subscriber line cards and in full featured digital telephone sets. the snic can be combined with the mt8971b/72b to implement an nt1 function(with biphase line code on the u interface) as shown in figure 16. it can also be combined with the mt8910 to implement an isdn nt1 function (with 2b1q line code on the u interface) as shown in figure 17. the mt8930c is con?gured in nt mode, acting as a master to the s- interface line, while the mt8971b/72b or the mt8910 operates in slave mode and derives its timing from the u-interface line originating from the central of?ce. for figure 16, communication between the two devices is done via the serial st- bus ports. control and status of the snic is communicated with the mt8971b/72b through the c-channel of the st-bus. figure 18 illustrates the use of the snic in conjunction with the mt9094 to implement a 2b+ d, isdn telephone set. the mt9094 provides such features as a/d and d/a conversion, handset interface, handsfree operation and tone ringer. pcm encoded voice is passed from the mt9094 to the snic via the st-bus port for transmission on one of the b-channels. the second b-channel is available for transmission of data. these two devices have been designed to connect together with virtually no interconnection components. both the mt8930c and mt9094 are controlled and monitored by a microprocessor to implement various features and control functions. signalling may be performed by scanning the keypad and generating appropriate messages to be packetized by the hdlc section of the snic and transmitted via the d- channel. a twelve segment, non-multiplexed lcd display can be connected directly to the s12-s1 outputs to provide various status and call progress indicators. it must be noted, that the pseudo-ternary line code will tolerate line reversals within the lrx and ltx pair between the nt and te. however, reversal of the te transmit pair between two or more tes will make the s-interface inoperable. in multidrop applications, a powered-off te must not load the line and prevent communications between the nt and other tes. to avoid such a situation, one mechanical relay should be used to disconnect the ltx pin and the lrx pin from the line transformers. interfacing to non-multiplexed busses the microprocessor interface for the snic was designed around a multiplexed bus architecture which may be found with most intel processors/ controllers or a few motorola processors. in the event that your choice of processors is restricted, a simple application circuit can convert the non- multiplexed bussing to that of a multiplexed architecture. figure 19 provides an to interface the mc6802 or the mc6809 microprocessors. figure 16 - nt1 function dsti dsto f0b c4b ms0 ms1 ms2 v ref v bias l out l in osc1 osc2 dsto dsti f0b c4b p/ sc nt rsti star c mode ltx lrx v bias mt8930c mt8971b/72b dc to dc converter +5v 2:1 +5v +5v +5v r tx 1:2* 1:2* r ? r ? 10k w 1.5 nf 22 nf 47 w 10.24 mhz xtal 33 pf 33 pf 0.33 m f 1.0 m f ? 100 w terminating resistor 390 w 0.33 m f 0.33 m f 10 m f
mt8930c 9-59 figure 17 - nt1 using the mt8910-1 (dslic) and mt8930c (snic) figure 18 - isdn digital telephone set termination network mh89101 l out+ l in+ l in- l out- c4b f0b dsti dsto c4b f0b dsto dsti ltx v bias lrx mt8910-1 dslic mt8930c nt mode power supply and power feed u reference point +5v microprocessor r tx v dd 2:1 2:1 r ? r ? 10 m f s reference point ? 100 w terminating resistor dsti dsto f0i c4i data1 sclk cs hspkr+ hspkr- m+ m- mic+ mic- spkr+ spkr- s12-1 k e y p a d display handset microphone speaker 8051 mt8930c mt9094 dsto dsti f0b c4b c mode data port irq lrx v bias ltx irq 10k +5v dc to dc converter r ? r ? 1:2 1:2 r tx v dd 2k w v dd 23 456 789 * # 0 ? 100 w terminating resistor +5v 1
mt8930c 9-60 ets 300-012 nt&te line interface figures 20, 21 and 22 show the recommended line interface circuits for meeting the ets 300-012 requirements. these circuits assume that test measurements are made using the "standard reference cord" which has the following speci?cations: c = 315pf to 350pf r = 2.7 w to 3.0 w z > 75 w length < 10m several types of transformers can be used: ? filtran tpw-3852-4 (figure 20) ? vac t60403-l4096-x028 (breakdown voltage 4kv) (figure 21) ? vac t60403-l4096-x027 breakdown voltage 2kv) (figure 21) ? vac t60403-l4096-x029 (breakdown voltage 4kv) (figure 22) ? vac t60403-l4096-x030 (breakdown voltage 2kv) (figure 22) l4096-x029 and l4096-x030 are equivalent to l4096-x028 and l4096-x027 with the exceptions of pin out; l4096-x029 and l4096-x030 are pin compatible with l4096-x028-80. in figure 20, t1, 2 (filtran tpw-3852-4) provides isolation, longitudinal balance, impedance matching and voltage level conversion. d5 and 6 (germanium) ensure that the pulse shape lies within the center of the various pulse templates. d1-4 protect the mt8930c from line transients. c2, 3 decouple the vbias voltage and optimize the receiver sensitivity. r1 and c4 make up a low-pass ?lter recommended for delaying the signal in te applications, this ?lter can also be used for nt applications allowing common hardware for te and nt applications. k1 isolates the mt8930c from the line for multidrop applications in cases where the device is powered down. l1 is 4-winding 5mh common mode choke to suppress emi on the 4-wire line. the tpw-3852-4 is available from: filtran ltd. 229 colonnade road nepean, ontario canada telephone: (613) 226-1626 figure 19 - interfacing to the mc6802 microprocessor mt8930c ad0-ad7 cs ds r/ w as dir b a g a b dir g qd address decoder v dd 74hct245 v dd 74hct245 mc6802 (mc6809) a0 - a7 vma d0 - d7 r/ w e extal (q) connections to interface to mc6809
mt8930c 9-61 in figure 21, two types of diodes (germanium 1n270 or schottky mbd301) can be used for d5,6. 1n270 will leave more margin for pulse template and longitudinal conversion loss. however, mbd301 will leave more margin for impedance template. all other components are as described previously for figure 20. the vac transformers are available from: germany vacuumschmelze gmbh postfach 22 53 d-63412 hanau telephone: (49) 6181 380 canada votron electronic ltd. 250 rayette road concord, ontario l4k 2g6 telephone: (905) 669-9870 usa vacuumschmelze corporation 4027 will rogers parkway oklahoma city, ok 73108 telephone: (405) 943-9651 proprietary nt&te line interface for proprietary applications, where stringent requirements such as ets 300-012 do not have to be met, the line interface circuit may be simpler and consequently less expensive. figure 23 shows such a line interface circuit. r1 should be chosen according to the transformer selected and the desired output signal level, typical values of r1 may vary from 30 w to 75 w . numerous types of transformers may be used, including the following: apc 8016d (dual with common mode choke) filtran tew-5660 (surface mount) filtran tpw-3852-4 (single) pulse pe-65495 (dual) vac l4097-x028-80 (single) in figure 22, everything is the same as in figure 21, except transformer pin out. figure 20 - ets 300-012 nt & te line interface for filtran tpw-3852-4 v dd c1 v dd ltx d5 d6 v dd d1 d2 5 4 3 t1 6 1 2 v bias v dd 5 4 3 l1 6 1 2 r2 r3 t2 k1 k1 v dd d3 d4 r1 lrx v ss c3 c4 mt8930c + c2 tx+ tx- rx- rx+ d7 k1 v dd parts list: c1, 3 = 0.1 m f ceramic c2 = 10 m f tantalum c4 = 22pf d1-4 = in914 d5, 6 = in270 germanium d7 = in4003 k1 = 2 form a or c relay (eg., aromat tq2e-5v) l1 = vac n4025-x034 r1 = 3k01 1% r2, 3 = 100 w 1% t1, 2 = filtran tpw-3852-4 6 7 9 10 5 4 2 1
mt8930c 9-62 figure 21 - ets 300-012 nt & te line interface for vac x027 or x028 figure 22 - ets 300-012 nt & te line interface for vac x029 or x030 v dd c1 v dd ltx d5 d6 v dd d1 d2 1 2 3 t1 4 5 6 v bias v dd 1 2 3 l1 4 5 6 r2 r3 t2 k1 k1 v dd d3 d4 r1 lrx v ss c3 c4 mt8930c + c2 tx+ tx- rx- rx+ d7 k1 v dd parts list: c1, 3 = 0.1 m f ceramic c2 = 10 m f tantalum c4 = 22pf d1-4 = in914 d5, 6 = in270 germanium or mbd301 schottky d7 = in4003 k1 = 2 form a or c relay (aromat tq2e-5v) l1 = vac n4025-x034 r1 = 3k01 1% r2,3 = 100 w 1% t1, 2 = vac t60403-l4096- x027 or vac t60403-l4096- x028 6 7 9 10 5 4 2 1 v dd c1 v dd ltx d5 d6 v dd d1 d2 6 1 t1 4 5 2 v bias v dd 6 1 l1 4 2 r2 r3 t2 k1 k1 v dd d3 d4 r1 lrx v ss c3 c4 mt8930c + c2 tx+ tx- rx- rx+ d7 k1 v dd parts list: c1, 3 = 0.1 m f ceramic c2 = 10 m f tantalum c4 = 22pf d1-4 = in914 d5, 6 = in270 germanium or mbd301 schottky d7 = in4003 k1 = 2 form a or c relay (aromat tq2e-5v) l1 = vac n4025-x034 r1 = 3k01 1% r2,3 = 100 w 1% t1, 2 = vac t60403-l4096- x029 or vac t60403-l4096- x030 3 3 5 6 7 9 10 5 4 2 1
mt8930c 9-63 figure 23 - proprietary nt & te line interface v dd c1 v dd ltx v dd d1 d2 t1 v bias v dd r3 r4 t2 v dd d3 d4 r1 r2 lrx v ss c3 mt8930c + c2 tx+ tx- rx- rx+ parts list: c1, 3 = 0.1 m f ceramic c2 = 10 m f tantalum d1-4 = in914 r1 = see circuit description r2 = 2k to 4k r3, 4 = 100 w t1, 2 = see circuit description
mt8930c 9-64 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * except for ck/nt pin. see below. ** including the transformer dc resistance. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings * parameters symbol min max units 1 supply voltage v dd -0.3 7.0 v 2 voltage on any i/o pin v i/o -0.3 v dd + 0.3 v 3 current on any i/o pin i i/o 20 ma 4 storage temperature t st -65 150 c 5 package power dissipation p d 1000 mw recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated characteristics sym min typ ? max units test conditions 1 supply voltage v dd 4.75 5.0 5.25 v 2 input high voltage* v ih 2.4 v dd v for 400mv noise margin 3 input low voltage* v il 0 0.4 v for 400mv noise margin 4 load resistance (ltx) r l 250** w with reference to v bias 5 load capacitance (ltx) c l 32 pf with reference to v bias 6 operating temperature t op -40 85 c dc electrical characteristics - voltages are with respect to ground (v ss ) unless otherwise stated characteristics sym min typ ? max units test conditions 1 supply current nt activated nt deactivated te activated te deactivated i ddna i ddnd i ddta i ddtd 14 8 16 10 20 11 25 14 ma ma ma ma outputs loaded outputs unloaded outputs loaded outputs unloaded 2 input high voltage except for pin ck/nt v ih 2.0 v digital inputs 3 input high voltage for pin ck/nt v ih 4 v digital input 4 input low voltage except for pin ck/nt v il 0.8 v digital inputs 5 input low voltage for pin ck/nt v il 1 v digital input 6 output high current i oh 10 15 ma v oh =2.4v digital outputs 7 output low current i ol 5 7.5 ma v ol =0.4v digital outputs 8 input leakage (except pin 8) i ii 10 m av in = v ss to v dd 9 input current for pin 8 25 m av in = v ss to v dd 10 output leakage high imped. i oz 10 m av out = v ss to v dd ac electrical characteristics - voltages are with respect to ground (v ss ) unless otherwise stated characteristics sym min typ ? max units test conditions 1 input voltage (lrx) v in 1.5 v peak with ref. to v bias 2 input current (lrx) i in 70 m av i =1.5vp ref. v bias @ f=0 - 100 khz 3 output voltage (ltx) v o 1.5 v ref. v bias , r l =250 w 4 output current (ltx) i o 7.5 ma v o =1.5vp ref. v bias , r l =250 w 5 input impedance (lrx) z in 20 k w f = 100 khz
mt8930c 9-65 ? timing is over recommended temperature & power supply voltages ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 22 - st-bus timing nt mode ac electrical characteristics ? - st-bus timing nt mode (ref. figure 22) characteristics sym min typ ? max units test conditions 1 f0b input pulse width t fpw 122 244 ns 2 frame pulse ( f0b) set-up time t fps 35 ns 3 frame pulse ( f0b) hold time t fph 50 ns 4 c4b input clock period t p4o 244 ns 5 c4b pulse width high or low t c4w 122 ns 6 c4b transition time t c4t 20 ns 7 f0od delay t dfd 20 87 ns 40 pf load 8 f0od pulse width t dfw 244 ns 9 serial input set-up time t sis 70 ns 10 serial input hold time t sih 0ns 11 serial output delay t sod 160 320 ns ns 50 pf load 50 pf load (hdlc connected to st-bus) 12 half input setup time t has 0ns 13 half input hold time t hah 200 ns st-bus bit cell f0b c4b f0od dsti dsto half v ih v il v ih v il v oh v ol v ih v il v oh v ol v ih v il t fpw t fps t p4o t c4w t c4t t c4w t dfd t fph t sis t sih t dfw t sod t has t hah
mt8930c 9-66 ? timing is over recommended temperature & power supply voltages ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 23 - st-bus timing te mode ac electrical characteristics ? - st-bus timing te mode (ref. figure 23) characteristics sym min typ ? max units test conditions 1 f0b output pulse width t fpw 244 ns 50 pf load 2 c4b to ( f0b) delay t cfd 10 50 ns 50 pf load 3 c4b to ( f0b) hold time t cfh 10 50 ns 50 pf load 4 c4b output clock period t p4o 244 ns 50 pf load 5 c4b pulse width high or low t c4w 110 122 ns 50 pf load (activated state) 6 c4b transition time t c4t 20 ns 50 pf load 7 f0od delay t dfd 10 50 ns 8 f0od pulse width t dfw 220 244 ns 9 serial input setup time t sis 150 ns 10 serial input hold time t sih 0ns 11 serial output delay t sod 125 ns 50 pf load 12 half output delay t had 150 ns 50 pf load f0b c4b f0od dsti dsto half v oh v ol v oh v ol v oh v ol v ih v il v oh v ol v oh v ol t fpw st-bus bit cell t cfd t cfh t p4o t c4w t c4w t c4t t dfd t sis t sih t dfw t sod t had
mt8930c 9-67 ? timing is over recommended temperature & power supply voltages ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 24 - intel bus interface timing (write cycle) figure 25 - intel bus interface timing (read cycle) ac electrical characteristics ? - intel bus interface timing (ref. figure 24 & 25) characteristics sym min typ ? max units test conditions 1 chip select setup time t css 10 ns 2 chip select hold time t csh 25 ns 3 address latch pulse width t alw 50 ns 4 address setup time t ads 20 ns 5 address hold time t adh 20 ns 6 data setup time - write t dws 35 ns 7 data hold time - write t dhw 20 ns 8 data output delay - read t dod 240 ns 50 pf load 9 data hold time - read t dhr 25 90 ns 50 pf load 10 write pulse width t wpw 60 ns 11 rd, wr delay t rwd 60 ns 12 read pulse width t rpw 240 ns 13 read setup time t rds 20 ns cs ale ad0-7 wr rd v ih v il v ih v il v ih v il v ih v il v ih v il address data in t css t csh t alw t ads t adh t rwd t dhw t wpw t rds t dws cs ale ad0-7 wr rd v ih v il v ih v il v i/oh v i/ol v ih v il v ih v il t csh t alw t ads t adh t dod t dhr t rds t css t rwd t rpw address data out
mt8930c 9-68 ? characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 26 - motorola bus interface timing ac electrical characteristics ? - motorola bus interface timing (ref. figure 26) characteristics sym min typ ? max units test conditions 1 chip select setup time t css 10 ns 2 chip select hold time t csh 10 ns 3 address strobe pulse width t asw 50 ns 4 data strobe setup time t dss 20 ns 5 data strobe hold t dsh 20 ns 6 data strobe pulse width - write - read t dsw 100 240 ns ns 7 read/write setup time t rws 40 ns 8 read/write hold time t rwh 10 ns 9 address setup time t ads 20 ns 10 address hold time t adh 20 ns 11 data setup time - write t dws 35 ns 12 data hold time - write t dhw 30 ns 13 data output delay t dod 240 ns 50 pf load 14 data hold time - read t dhr 25 90 ns 50 pf load cs as ds r/ w ad0 -ad7 (write) ad0 -ad7 (read) v ih v il v ih v il v ih v il v ih v il v ih v il v i/oh v i/ol t css t csh t asw t dss t dsh t dsw t rws t rwh t ads t adh t dws t dhw t ads t adh t dod t dhr address data output address data input
mt8930c 9-69 ? characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 27 - controllerless mode timing ? characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 28 - int & rsti timing ac electrical characteristics ? - controllerless mode timing (ref. figure 27) characteristics sym min typ ? max units test conditions 1c mode inputs setup time (te mode) t cis 120 ns 2c mode inputs setup time (nt mode) t cis 120 ns 3c mode inputs hold time (te mode) t cih 120 ns 4c mode inputs hold time (nt mode) t cih 120 ns 5c mode outputs delay (te mode) t cod 240 ns 50 pf load 6c mode outputs delay (nt mode) t cod 240 ns 50 pf load ac electrical characteristics ? - irq, rsti timing (ref. figure 28) characteristics sym min typ ? max units test conditions 1 interrupt release delay t ird 100 ns 2 reset pulse width t rsw 1 m s f0b c4b inputs outputs controllerless inputs include: v ih v il v ih v il v ih v il v oh v ol t cis t cih t cod mfr (nt mode) mch (te mode) m/s (nt mode) ar dr controllerless outputs include: is0 & is1 mfr (te mode) mch (nt mode) m/s (te mode) ds/ rd irq rsti v ih v il v oh v ol v ih v il t ird t rsw
mt8930c 9-70 notes:
package outlines plastic j-lead chip carrier - p-suf?x f d 1 d h e 1 i a 1 a g d 2 e e 2 dim 20-pin 28-pin 44-pin 68-pin 84-pin min max min max min max min max min max a 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.200 (5.08) 0.165 (4.20) 0.200 (5.08) a 1 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.130 (3.30) 0.090 (2.29) 0.130 (3.30) d/e 0.385 (9.78) 0.395 (10.03) 0.485 (12.32) 0.495 (12.57) 0.685 (17.40) 0.695 (17.65) 0.985 (25.02) 0.995 (25.27) 1.185 (30.10) 1.195 (30.35) d 1 /e 1 0.350 (8.890) 0.356 (9.042) 0.450 (11.430) 0.456 (11.582) 0.650 (16.510) 0.656 (16.662) 0.950 (24.130) 0.958 (24.333) 1.150 (29.210) 1.158 (29.413) d 2 /e 2 0.290 (7.37) 0.330 (8.38) 0.390 (9.91) 0.430 (10.92) 0.590 (14.99) 0.630 (16.00) 0.890 (22.61) 0.930 (23.62) 1.090 (27.69) 1.130 (28.70) e 0 0.004 0 0.004 0 0.004 0 0.004 0 0.004 f 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) g 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) h 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) i 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) for d & e add for allowable mold protrusion 0.010" e: (lead coplanarity) general-10
package outlines plastic dual-in-line packages (pdip) - e suf?x note: controlling dimensions in parenthesis ( ) are in millimeters. dim 8-pin 16-pin 18-pin 20-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) a 2 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) c 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356) d 0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) e 1 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) l 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) e b 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) e c 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b e c general-8
package outlines plastic dual-in-line packages (pdip) - e suf?x dim 22-pin 24-pin 28-pin 40-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35) a 2 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) c 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) d 1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) e 0.290 (7.37) .330 (8.38) e 1 0.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) e 1 0.246 (6.25) 0.254 (6.45) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.400 bsc (10.16) 0.600 bsc (15.24) 0.600 bsc (15.24) 0.600 bsc (15.24) e a 0.300 bsc (7.62) e b 0.430 (10.92) l 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) a 15 15 15 15 e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b a shaded areas for 300 mil body width 24 pdip only
m mitel (design) and st-bus are registered trademarks of mitel corporation mitel semiconductor is an iso 9001 registered company copyright 1999 mitel corporation all rights reserved printed in canada technical documen t a tion - n o t for resale world headquarters - canada tel: +1 (613) 592 2122 fax: +1 (613) 592 6909 north america asia/paci?c europe, middle east, tel: +1 (770) 486 0194 tel: +65 333 6193 and africa (emea) fax: +1 (770) 631 8213 fax: +65 333 6192 tel: +44 (0) 1793 518528 fax: +44 (0) 1793 518581 http://www.mitelsemi.com information relating to products and services furnished herein by mitel corporation or its subsidiaries (collectively mitel) is believed to be reliable. however, mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by mitel or licensed from third parties by mitel, whatsoever. purchasers of products are also hereby noti?ed that the use of product in certain ways or in combination with mitel, or non-mitel furnished goods or services may infringe patents or other intellectual property rights owned by mitel. this publication is issued to provide information only and (unless agreed by mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, their speci?cations, services and other information appearing in this publication are subject to change by mitel without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speci?c piece of equipment. it is the users responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in signi?cant injury or death to the user. all products and materials are sold and services provided subject to mitels conditions of sale which are available on request.

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